Power management system

ABSTRACT

According to one embodiment of the present invention, there is provided a power management system for use in a computer system having a memory system incorporating a non-volatile memory and a controller which presents the logical characteristics of a disc storage device to a host, the power management system comprising means for monitoring the operational activity levels within at least some of the components of the controller and arranged, in response to the monitored levels, to vary the power consumed by selected components of the controller.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of the priority date of myearlier filed British Application No. 0123421.0, entitled “PowerManagement System”, filed on Sep. 28, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates generally to a power management system formanaging power used and energy consumed in a computer system,particularly a portable computer system where there is often a limit tothe peak power that can be supplied and where the energy is usuallyprovided by batteries which have a shorter life if required to deliverincreased energy and particularly to a flash disc device which is amemory system having a controller which presents the logicalcharacteristics of a disc storage device to a host, but, which uses anon-volatile semiconductor memory device as its physical storage medium.

[0004] 2. Description of the Prior Art

[0005] Minimizing peak power (where power is energy per unit time) andminimizing energy consumption are sometimes conflicting aims. Tominimize the peak power drawn by a Flash Storage System may require thatthe Flash Storage System takes longer to perform its operations, whichcan lead to higher energy dissipation since the system is active over alonger period, though at a lower power over this period.

[0006] The standard Flash Controller includes a number of hardwareblocks. These blocks include a Host Interface Block, a Flash InterfaceBlock and a Microprocessor Block, which are connected to memories via aSystem Bus. Each of these hardware blocks consumes energy within theFlash Controller. The Host Interface and Flash interface blocks alsoconsume energy on external interfaces. To minimize the energyconsumption of the whole computer system requires the minimization ofenergy consumption within the Flash Controller itself, within the Flashmemory, and on the Flash and Host Interfaces.

[0007] Thus, a need arises to obviate or mitigate at least one of theaforementioned problems.

SUMMARY OF THE INVENTION

[0008] According to a first aspect of the invention there is provided apower management system for use in a computer system having a memorysystem incorporating a non-volatile memory and a controller whichpresents the logical characteristics of a disc storage device to a host,the power management system comprising means for monitoring theoperational activity levels within at least some of the components ofthe controller and arranged, in response to the monitored levels, tovary the power consumed by selected components of the controller.

[0009] Preferably the power management system further comprises at leastone power management algorithm which is implemented within firmware ofthe power management system.

[0010] In another of its aspects the present invention comprises anon-volatile memory system having a controller incorporating a pluralityof components and which presents the logical characteristics of a discstorage device to a host, where the controller incorporates a powermanagement system having means for monitoring the operational activitylevels within at least some of the components of the controller, saidmeans being arranged, in response to the monitored levels, to vary thepower consumed by selected components of the controller.

[0011] The power management system may be embodied in a discrete systemmanager or in a distributed manner through components of the controller.

[0012] Preferably the power management system generates the main clocksignals for the controller and determines which are active and thefrequency of such active clock signals.

[0013] The foregoing and other objects, features and advantages of thepresent invention will be apparent from the following detaileddescription of the preferred embodiments which make reference to severalfigures of the drawing.

IN THE DRAWINGS

[0014]FIG. 1 illustrates a computer system incorporating a powermanagement system in accordance with the present invention;

[0015]FIG. 2 illustrates the power management system of FIG. 1 ingreater detail; and

[0016]FIG. 3 illustrates an example of the way in which the controller16 of FIG. 1 switches between different power levels during theexecution of a Write Sector command from a host.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] As is shown in FIG. 1, a computer system 10 comprises a flashmemory 14, a flash controller 16 and host system 12. The controller 16comprises a host interface block 16, a microprocessor 24, a flashinterface block 22, an SRAM 28, a ROM 30, all of which are connected toa memory access control structure or system bus 21 in a manner which iswell known in the art and which enables the memory system 16, 14, topresent to the host system 12 the logical characteristics of a discstorage device.

[0018] Controller 16 of a system 10 additionally incorporates a powermanagement system in the form of a system manager 20.

[0019] Having a discrete System Manager Block 20 simplifies the designand explanation of the power management features, however, the featuresto be described could equally be distributed and incorporated into otherblocks within the hardware of controller 16. The term ‘system manager’is intended to embrace both the distributed and the discretearrangements.

[0020] The System Manager 20 is concerned with the control of reset,timing and interrupt signals within the controller 16, and the controllogic for these signals may also be incorporated within the SystemManager, however, this is not necessary for achieving power management.

[0021]FIG. 2 shows the structure of the system manager 20. The systemmanager 20 comprises a system manager bus interface and control logicblock 30 which connects the system manager 20 to the system bus 21 viabus interface 22. The system manager 20 also includes an event monitorblock 32, a microprocessor throttle control block 34, system clockcontrol block 36, a phase locked loop (PLL) block 38, clock oscillatorblock 40 power-down controller (PDC) level 1 block 42, PDC level 2 block44, PDC level 3 block 46 and PDC level block 48.

[0022] The System Manager 20 generates clock signals for the rest of thecontroller 16. Though one clock is shown, multiple clocks for differentparts of the controller 16 may be generated. Whether a clock is enabled,and its frequency, are determined by power management features. Thesystem Manager 20 also generates other control signals to controlactivity within the Flash Controller 16. One signal enables themicroprocessor 24. Firmware reads and writes to memory-mapped registerswithin the system manager 20 across the interface 30 via the system bus21.

[0023] The Event Monitor 32 takes signals from a number of event sources29 within the Flash Controller 16. These event sources 29 indicate whensignificant system events have occurred within other blocks of thecontroller 16 such as the Flash and Host Interface Blocks 22, 26 or theMicroprocessor 24. For example, the flash and host interface blocks 22,26 typically indicate when certain operations have completed via thesesignals. Events that are used to generate processor interrupts orwake-up from a power-down state are listed in Table 3. Synchronousevents require the system clock to be running and so will not begenerated when the controller is in power-down level 2 or higher. Theprocessor 24 typically indicates when a special event has occurred, suchas a request to enter a Debug or Test Mode. The event monitor 32 andsystem manger bus interface and control logic block 30 communicate viafour channels which carry the signals EVT_CLEAR 31A, EVT_LEVEL 31B,EVT_STATUS 31C, and EVT_WAKEUP 31D.

[0024] The Event Monitor 32 feeds the existing level of these events tothe Bus Interface and control logic block 30 on the EVT_LEVEL signal,which is composed of one bit per event. The event source signals can bede-asserted by the source at any time. In some cases, when thecontroller 16 is in a low-power state, it may not be able to respond tothe EVT_LEVEL signal immediately, and could miss an event. Thus, theevent monitor 32 provides a second copy of the events called EVT_STATUS,that cannot be de-asserted by the source of the event, but can be set(even when the rest of the system is in a low-power state). An event inEVT_STATUS can only be de-asserted by the Bus Control Logic Block 30asserting the appropriate bit on the EVT_CLEAR signal or a System Reset.

[0025] During certain low-power modes, the Event Monitor 32 may be theonly active part of the system manager 20. If required, it outputs asignal 31E to the rest of the System Manager 20 called WAKEUP, whichcauses the rest of the system manager 20 to exit from a low-power mode.The WAKEUP signal is asserted when an event is asserted on EVT_STATUSand the corresponding event bit is asserted on EVT_WAKEUP. Thus, theGBus Interface block 30 can control which events cause the manger 20 towake-up. firmware via the Bus Interface 30 block reads the values ofboth EVT_LEVEL and EVT_STATUS and asserts EVT_CLEAR and EVT_WAKEUP.

[0026] Included within the System Manager 20 are blocks 36, 38, 40 forgenerating the main clock signals for the controller 16 and for enablingother blocks within the controller 16 such as the Microprocessor 24.

[0027] The clock generation chain consists of clock oscillator module40, that generates the fundamental clock for the controller 16 (namedOSC_CLK). The frequency of this clock is normally determined by externalcomponents such as a Quartz Crystal or a Resistor-Capacitorcharging/discharging circuit. The next stage in the clock generation isthe PLL (Phase Locked Loop) block 38 which takes the fundamental clockfrequency OSC_CLK and multiplies it by a factor to generate the signalPLL_CLK. Finally, this goes into the system clock control block 36,which controls the distribution of the clock to the rest of thecontroller 16.

[0028] The System Manager 20 has four power-down modes that are used tocontrol which clock signals are active within the controller 16.Successive Levels of Power-Down mode turn off more functionality withinthe controller 16 to save power. The term Power-Down Mode 0 is used todescribe normal system operation when all parts of the controller 16 areactive. Table 1 illustrates how functionality of the controller 16 isprogressively turned off to save power with successive Power-Down Modes.

[0029] In Power-Down Mode 1 which is determined by block 42, theMicroprocessor 24 is disabled in a controlled fashion, so that otherblocks within the controller 16 such as the Flash and Host InterfaceBlocks 22, 26 can continue to access memory 14 and perform theirfunctions. The enable signal to the processor 24 is turned off using theMP_ENABLE signal from block 42 that feeds into the Processor ThrottlingBlock 34.

[0030] In Power-Down Mode 2 which is determined by block 44, the SystemClock 36 is disabled using the CLK_ENABLE signal from block 44.Functions within the controller 16 that rely on the system clock beingenabled are disabled and their power dissipation reduced or eliminated.A result of this is that the main system bus 21 will be disabled so thatcommunication between blocks within the controller 16 across the bus 21will be disabled.

[0031] In Power-Down Mode 3 which is determined by block 46, the PLL 38is disabled using the PLL_ENABLE signal from block 46. PLL 38 may take acertain time to synchronize with the OSC_CLK signal from oscillator 40,so a synchronization delay is usually required when the controller ispowering up from Power-Down Mode 3 to Power-Down Mode 2.

[0032] In Power-Down mode 4 which is determined by block 48, the clockoscillator 40 is disabled using the OSC_ENABLE signal from block 48. Theclock oscillator 40 may take a certain time to start oscillating againdepending on the nature of the external components used to determine theclock frequency, so a delay is required when the controller is poweringup from Power-Down Mode 4 to Power-Down Mode 3.

[0033] As regards sequencing of power-down and power-up each PDC 42, 44,46, 48 receives a request for entry to a power-down mode on a PDOWNsignal or entry to a power-up mode on the PUP signal. For example, thefirst PDC 42 will power-down the part of the controller 16 that itcontrols and then if this is not the target Power-Down Mode (asindicated on the PMODE signal issued by block 30), it will assert itsPDOWN signal to the next PDC 44 so that it should power-down and so on.

[0034] When the Event Monitor 32 asserts the WAKEUP signal 31E, thePDC's sequentially from the PDC of the target Power-Down Mode willwake-up the part of the controller 16 that it is responsible for. If adelay is required before this part of the controller 16 is ready thenthe PDC's ensure that this delay is met. The length of the delay may beconfigured Firmware writing to registers within the Bus Interface andControl Logic 30. The value of these registers is passed onto theappropriate PDC, which alters the Power-Up delay to reflect the registervalue. These signals indicating the length of the delay are notillustrated. Finally the PDC asserts its Power-Up output PUP whichcauses the next PDC in the chain to wake-up in a similar fashion.

[0035] Initially entry to a power-down mode is made by firmware writingto a register within the System Manager Bus Interface and Control Logicblock 30, which indicates the desired Power-Down Mode. This causes thePMODE signal to indicate the target power-down level, and the PDOWN0signal to be asserted which initiates the entry into the Power-DownMode.

[0036] The modular structure of one PDC 42, 44, 46, 48 for each sectionof the clock generation and processor control 34, 36, 38, 40 allows thestructure to be easily adapted for different clock generationstructures. In addition, this structure is robust in that it guaranteesthat the controller 16 is powered-down and powered-up in an orderlymanner, so that, for example, the processor 24 is not powered-up beforethe system clock signal is enabled.

[0037] A second power-management feature of the manager 20 is theability to change the clock frequency by changing the multiplicationfactor that relates the PLL 38 input frequency to its output frequency.Lowering the Clock frequency lowers the power dissipation within thecontroller l6, but, also can reduce the data transfer performance of thecontroller 16.

[0038] To vary the PLL multiplication factor firmware writes to aregister within the Bus Interface and Control Logic block 30 which setsthe value of PLL_FACTOR that indicates the PLL Multiplication Factor. Insome cases, Firmware may want the value of PLL_FACTOR to be reset to acertain value when a system event occurs. For example, the Firmware setsa low clock frequency to reduce power, but it then wants to process aninterrupt quickly, the firmware may not want to continue to run at thelow clock frequency. However, it takes a certain amount of time to writeto the register that determines PLL_FACTOR. To overcome this problem,the firmware can set a flag within the Bus Interface and Control Logicblock 30 which will cause the block 30 to reset the PLL_FACTOR whencertain events occur as indicated by the Event Monitor 32.

[0039] The Microprocessor 24 is often the main source of powerdissipation in the Controller 16 as it consumes power itself and also isthe main source of memory access requests within the Controller 16. Toallow the power consumption of the Microprocessor 24 to be controlledthe System Manager 20 includes a Microprocessor Throttle Block 34.

[0040] The Throttle Block 34 controls how often the Microprocessor 24 isenabled. The fewer clock cycles that the Microprocessor 24 is enabledfor, the lower the power it consumes. The mechanism used to achievedisablement of the Microprocessor 24 can vary. For example, the outputof throttle block 34 can be used directly to disable the Microprocessor24 or to switch off the clock signal within controller 16 to theMicroprocessor 24. Alternatively, the output of the throttle block 34can be used to deny access of the Microprocessor 24 to the Main-SystemBus 21, thus preventing it from fetching instructions and causing it tohalt.

[0041] The Throttle Block 34 takes two inputs: one is MP_ENABLE from thePDC 42 for the Power-Down Mode 1. The MP_ENABLE signal is used tocompletely disable the Microprocessor 24 when Power-Down Mode 1 isentered. The other input to the Throttle Block 34 is THROTTLE whichconsists of three values M, S and B which determine the proportion oftime that the Microprocessor 24 is enabled. The value of THROTTLE can bechanged by the firmware writing to registers within the Bus Interfaceand Control Logic Block 30.

[0042] The values M (Mark) and S (Space) determine the ratio of clockcycles for which the Microprocessor 24 is enabled and disabled. The Bvalue determines the minimum number of clock cycles in a row theMicroprocessor 24 will be enabled or disabled for. This allows theMicroprocessor 24 to gain access to the Memory 14 for a minimum numberof clock cycles, since there would be overhead and inefficiencies whenenabling and disabling the Microprocessor 24 for too few clocks cycles.

[0043] Thus, the values M, S and B indicate that the Microprocessor 24is enabled for M*B clock cycles from every (M+S)*B clock cycles. Thehardware interleaves M blocks of cycles with S blocks of cycles in anoptimum way to minimize long sequences of cycles with the Microprocessor24 disabled, which could reduce the Microprocessor 24 responsiveness toevents such as interrupts.

[0044] The pattern set by M, S, and B is as follows. The pattern startswith a block of B clock cycles with the Microprocessor 24 being enabledand then B clock cycles this with the Microprocessor 24 being disabled.The alternation of blocks of the Microprocessor 24 being enabled anddisabled repeats up to the minimum value from M and S. If M=S then thepattern now repeats, otherwise, if M>S, then the Microprocessor 24 isenabled for M−S blocks of B clock cycles and then the pattern repeats,but, if M<S then the Microprocessor 24 is disabled for S−M blocks of Bclock cycles and then the pattern repeats.

[0045] The hardware always ensures that the first block within a patternof enabling and disabling the Microprocessor 24 has the Microprocessor24 enabled regardless of the value of M, thus setting M=0 is equivalentto M=1 in order to prevent the Microprocessor 24 being never enabled.The hardware also interprets the value of B=0 as the maximum block sizeallowed by the hardware.

[0046] Some examples of the patterns possible of the hardware enablingand disabling the Microprocessor 24 for different values of M, S and Bare shown in Table 2.

[0047] Other schemes for defining the ratio of cycles for which themicroprocessor 24 is enabled and disabled are possible.

[0048] As with the PLL Multiplication Factor feature discussedpreviously, it is useful to allow Firmware to allow the MicroprocessorThrottle 34 to reset the time for which the Microprocessor 24 is enabledto its maximum value when certain system events occurs, to allow forfast reaction to controller events. Firmware can write to a registerwithin the Bus Interface and Control Logic block 30 to enable thisfeature.

[0049] It will be appreciated that the Flash Interface Block 22 is nonstandard in that it incorporates features to operate with a range ofdifferent main system clock frequencies, since the main clock frequencyof the controller 16 may be changed to reduce power consumption byoperation of blocks 36, 38 of the system manager 20.

[0050] If the main clock frequency of the flash controller is changedthen this will affect the timing of signals generated by the FlashInterface Block 22. If the clock frequency is increased then the timingof signals on the flash interface may become too quick for the Flashmemory 14. If the clock frequency is decreased then the transfer rate ofdata to and from the Flash memory 14 will be reduced.

[0051] If the Flash Interface 22 is a major source of power dissipation,then it may be advantageous to reduce the transfer rate on the interfaceto reduce peak power consumption, but this reduces the data transferrate to and from the Flash memory 14.

[0052] Accordingly, to support these power management modes, the FlashInterface Block 22 is designed to allow the timing of signals to andfrom the Flash memory 14 to be changed relative to the main controllersystem clock. Two features in the Flash Interface Block 22 areincorporated to support this. The first feature is a frequency dividercircuit that is placed on the main clock that supplies the basic timingreference for the signals on the Flash interface 22. This allows thespeed of the Flash Interface to be reduced to reduce peak powerconsumption, without affecting the frequency of the main clock. Thesecond feature is the timing of signals in the Flash interface 22 can becontrolled on a clock cycle by clock cycle basis. When the main clockfrequency is decreased; this allows the timing of signals to be madequicker by reducing the number of clock cycles for which a signal on theFlash Interface is asserted or de-asserted.

[0053] Finally, the Flash Interface Block 22 is designed so that it canuse the power management features within the Flash memory 14 whichrequires that Flash memory select signal to be taken to a voltage closeto that of the power supply rail to engage a low power mode.

[0054] It will further be understood that the host interface block 26 isdifferent from the flash interface block 22, in the most actions on thehost interface block 26 are initiated and timed by the host 12 and notby the controller 15. Many host interface protocols allow the FlashStorage System 14, 16 to indicate at system power-up what host interfacetiming will be used, but do not allow this timing to be changed later.

[0055] Though in most Host interface protocols, the data transfer rateto and from the Flash Storage System 14, 16 is determined by the host12, most host interface transfer protocols allow the Flash StorageSystem 14, 16 to indicate when it is ready to accept the transfer ofdata or of a command. The Flash Controller 16 uses this feature of thehost interface 26 to control the rate of data and command transfer andthus minimize peak power though this reduces system performance. Tosupport this, the Host Interface block 26 needs to be flexible in whenit asserts signals that say if it is ready to accept a command or do adata transfer. If features are incorporated to let hardwareautomatically set these signals, then the automatic setting of thesesignals should configurable, so that flags can be set under directFirmware control if necessary for power management.

[0056] If the protocol allows for the basic timing of a data or commandtransfer to be slowed down by asserting signals on the interface 26during the transfer then these should also be settable by Firmware toallow the transfer rate to be reduced.

[0057] Reference has been made to firmware that has to utilize the powermanagement features within the flash controller hardware to minimizepower consumption with minimal impact or performance. This will now beexplained.

[0058] If at a point within the firmware, the firmware has to stop andwait for an event monitored by the Event Monitor 32, then the firmwareenables the system manager 20 to wake-up on this event and then enter apower-down mode. The Power-Down Mode powered-down to is determined byactivity in other parts of the controller 16. For example, if the Hostor Flash interface 26, 22 need the clock to be running to transfer datathen Power-Down Level 1 is the maximum level that can be entered. Higherpower down levels can be entered if no such constraint exists, but maybe limited by the time taken for the Oscillator 40 and PLL 38 topower-up.

[0059] Other events that are required to interrupt the processor 24 alsotrigger the system manager 20 to wake-up. If the system manager 20 iswoken-up by an interrupt event, it then responds to the interrupt andthen the Firmware returns to the Power-down mode selected, if the systemevent being waited for has not occurred.

[0060] Examples of doing this are events such as waiting for the host 12to issue a command or transfer data, or waiting for Flash memory 14 tocomplete an operation.

[0061] Events within the controller 16 that are not monitored by theEvent Monitor 32 cannot cause the system manager 20 to wake-up. In thesecases the Microprocessor 24 has to wait, polling a register until theevent occurs. In this mode, the Microprocessor 24 must be active, but,need not run at full speed.

[0062] Accordingly using the Microprocessor Throttling mechanism ofblock 34 can reduce power consumption in this case by reducing thefrequency of polling the register. Also, when reducing the clockfrequency will not affect the performance of other parts of thecontroller 16 then the PLL multiplication factor of block 38 can bereduced. When the event being polled for has occurred, the firmware canreturn the controller 16 to its normal operating frequency.

[0063] When firmware determines that it needs to limit power consumptionon the Host Interface Block 26, then it can reduce the power beingconsumed by indicating to the Host 12 that it is busy, even when it hasactually finished an operation or is ready to accept data. During thistime, the controller 16 can perform other operations, or the controller16 can enter a Power-Down Mode for a period of time to lower powerconsumption and trigger the system manager 20 to wake-up after aspecified time by using an event triggered by a timer within the FlashController 16. At this point, the controller 16 can release busy andcontinue operation. As an alternative to asserting busy, the controller16, if the host interface transfer protocol permits, can slow sown thehost transfer timing. This allows the host 12 to continue data transferbut at a reduced rate.

[0064] When the controller cycle time is changed to reduce power,Firmware may choose to adjust the timing of the Flash interface 22 touse fewer clock cycles to ensure that the transfer rate to memory 14 ismaintained.

[0065] If Firmware wants to reduce power consumption specifically on theFlash interface 22 then it can lengthen the timing of commands on theFlash Interface 22, though this will reduce the transfer rate to memory14. One example, of lengthening Flash Commands is when polling thestatus of the memory 14. Firmware can lengthen the timing of the pollingcommand, and then set the Flash Interface 22 to trigger an event whenthe Polling command has finished. Firmware can then go to sleep for theduration of the polling command.

[0066] When Firmware enters sections of code that requires theMicroprocessor 24 to be active for a long period of time, then peakpower consumption can be reduced by using the Microprocessor ThrottleMechanism of block 34 and the PLL Multiplication Factor of block 38.

[0067] An example of the way in which the controller switches betweendifferent power levels during the execution of a Write Sector commandfrom a host is given with reference to FIG. 3. The relative levels ofthe different power levels are for illustration only. In this example,the controller does not need to respond rapidly to host commands, andthe startup times of clock oscillator 40 and phase locked loop 38 duringwake-up from power-down levels 4 and 3 are not important. If fastresponse to a host command is required, it might not be possible toswitch to power-down level 4 when the host interface is in the idlestate.

[0068] At time A the host writes a command to the controller, whichgenerates event 4 shown in Table 3 and causes the controller to wake-upthrough levels 3, 2 and 1 before the processor starts executing in level0.

[0069] The processor clears the host command event and sets up the DMAhardware to allow the host to transfer data to the controller. Once theDMA is set up, the controller is put into power-down level 1 at time B.It is not possible to enter a higher power down level as the MDAtransfer requires that the system clock is running.

[0070] When the host transfers the required data at time C, event 5 isgenerated and wakes up the controller to power-down level 0. Theprocessor now sets up the Flash Interface Control to transfer the datato Flash memory and then reverts to power-down level 1 at time D. Again,a higher power-down mode cannot be used because the transfer to Flashmemory requires that the system clock is running.,

[0071] When the data transfer to Flash memory completes at time E, event7 is generated. The controller again wakes up to power down level 0. Theprocessor checks that the transfer was successful, starts the Flashprogramming operation and then enters power-down level 2 at time F,which halts the system clock.

[0072] At time G, the Flash programming operation completes and theFlash busy line makes a low to high transition, which generates event 6.The controller wakes up through power-down level 1 to power-down level0. The processor checks that the programming operation was successfuil,sets up the response to the host and powers-down to level 4 at time H.

[0073] Although the present invention has been described in terms ofspecific embodiments it is anticipated that alterations andmodifications thereof will no doubt become apparent to those skilled inthe art. It is therefore intended that the following claims beinterpreted as covering all such alterations and modification as fallwithin the true spirit and scope of the invention.

What is claimed is:
 1. A power management system for use in a computersystem comprising: A memory system including, A non-volatile memory; andA controller coupled to the non-volatile memory representing the logicalcharacteristics of a disc storage device to a host and including powermanagement means for monitoring the operational activity levels withinat least some of the components of the controller and arranged, inresponse to the monitored levels, to vary the power consumed by selectedcomponents of the controller.
 2. A power management system as recited inclaim 1 wherein the system is embodied in a discrete system manager.